国产人妻人伦精品_欧美一区二区三区图_亚洲欧洲久久_日韩美女av在线免费观看

合肥生活安徽新聞合肥交通合肥房產生活服務合肥教育合肥招聘合肥旅游文化藝術合肥美食合肥地圖合肥社保合肥醫院企業服務合肥法律

代做CS 211: Computer Architecture

時間:2024-04-15  來源:合肥網hfw.cc  作者:hfw.cc 我要糾錯



CS 211: Computer Architecture, Spring 2024
Programming Assignment 5: Simulating Caches (100 points)
Instructor: Prof. Santosh Nagarakatte
Due: April 25, 2024 at 5pm Eastern Time.
Introduction
The goal of this assignment is to help you understand caches better. You are required to write a
cache simulator using the C programming language. The programs have to run on iLab machines.
We are providing real program memory traces as input to your cache simulator.
No cheating or copying will be tolerated in this class. Your assignments will be automatically
checked with plagiarism detection tools that are powerful. Hence, you should not look at your
friend’s code or use any code from the Internet or other sources such as Chegg/Freelancer. We
strongly recommend not to use any large language model and use the code sample provided by
it as it will likely trigger plagiarism violations. All violations will be reported to office of student
conduct. See Rutgers academic integrity policy at:
http://academicintegrity.rutgers.edu/
Memory Access Traces
The input to the cache simulator is a memory access trace, which we have generated by executing
real programs. The trace contains memory addresses accessed during program execution. Your
cache simulator will have to use these addresses to determine if the access is a hit or a miss, and
the actions to perform in each case. The memory trace file consists of multiple lines. Each line of
the trace file corresponds to a memory access performed by the program. Each line consists of two
columns, which are space separated. First column lists whether the memory access is a read (R)
or a write (W) operation. The second column reports the actual 48-bit memory address that has
been accessed by the program. Here is a sample trace file.
R 0x9cb3d40
W 0x9cb3d40
R 0x9cb3d44
W 0x9cb3d44
R 0xbf8ef498
Part One - One Level Cache - 50 points
You will implement a cache simulator to evaluate different configurations of caches. The followings
are the requirements for the first part of the cache simulator.
1
• Simulate only one level cache; i.e., an L1 cache.
• The cache size, associativity, the replacement policy, and the block size are input parameters.
Cache size and block size are specified in bytes.
• You have to simulate a write through cache.
• Replacement Algorithm: You have to support two replacement policies. The two replacement
policies are: First In First Out (FIFO) and Least Recently Used (LRU).
Next, you will learn more about cache replacement policies.
Cache Replacement Policies
The goal of the cache replacement policy is to decide which block has to be evicted in case there is no
space in the set for an incoming cache block. It is always preferable – to achieve the best performance
– to replace the block that will be re-referenced furthest in the future. In this assignment, you will
use two different ways to implement the cache replacement policy: FIFO and LRU.
FIFO
When the cache uses the FIFO replacement policy, it always evicts the block accessed first in the
set without considering how often or how many times the block was accessed before. So let us say
that your cache is empty initially and that each set has two ways. Now suppose that you access
blocks A, B, A, C. To make room for C, you would evict A since it was the first block to be brought
into the set.
LRU
When the cache used the LRU replacement policy, it discards the least recently used items first.
The cache with an LRU policy has to keep track of all accesses to a block and always evict the
block that been used (or accessed) least recently as the name suggests.
Cache Simulator Interface
You have to name your cache simulator first. Your program should support the following usage
interface:
./first <cachesize> <assoc:n> <cache policy> <block size> <trace file>
where:
• The parameter cache size is the total size of the cache in bytes. This number should be a
power of 2.
2
• The parameter assoc:n specifies the associativity. Here, n is a number of cache lines in a set.
• The parameter cache policy specifies the cache replacement policy, which is either fifo or
lru.
• The parameter block size is a power of 2 that specifies the size of the cache block in bytes.
• The parameter trace file is the name of the trace file.
Simulation Details
• When your program starts, there is nothing in the cache. So, all cache lines are empty.
• You can assume that the memory size is 248 . Therefore, memory addresses are at most 48
bit (zero extend the addresses in the trace file if they are less than 48-bit in length).
• The number of bits in the tag, cache address, and byte address are determined by the cache
size and the block size.
• For a write-through cache, there is the question of what should happen in case of a write
miss. In this assignment, the assumption is that the block is first read from memory (i.e.,
one memory read), and then followed by a memory write.
• You do not need to simulate data in the cache and memory in this assignment. Because,
the trace does not contain any information on data values transferred between memory and
caches.
Sample Run
Your program should print out the number of memory reads (per cache block), memory writes (per
cache block), cache hits, and cache misses. You should follow the exact same format shown below
(no space between letters), otherwise, the autograder can not grade your program properly.
./first ** assoc:2 fifo 4 trace1.txt
memread:336
memwrite:334
cachehit:664
cachemiss:336
The above example, simulates a 2-way set associate cache of size ** bytes. Each cache block is 4
bytes. The trace file name is trace1.txt.
Note: Some of the trace files are quite large. So it might take a few minutes for the autograder to
grade all testcases.
3
Part II - Two Level Cache - 50 points
Most modern CPUs have multiple level of caches. In the second part of the assignment, you have
to simulate a system with a two-level of cache (i.e., L1 and L2). Multi-level caches can be designed
in various ways depending on whether the content of one cache is present in other levels or not.
In this assignment you implement an exclusive cache: the lower level cache (i.e., L2) contains only
blocks that are not present in the upper level cache (i.e., L1).
Exclusive Cache
Consider the case when L2 is exclusive of L1. Suppose there is a read request for block X. If the
block is found in L1 cache, then the data is read from L1 cache. If the block is not found in the
L1 cache, but present in the L2 cache, then the cache block is moved from the L2 cache to the L1
cache. If this causes a block to be evicted from L1, the evicted block is then placed into L2. If the
block is not found in either L1 or L2, then it is read from main memory and placed just in L1 and
not in L2. In the exclusive cache configuration, the only way L2 gets populated is when a block is
evicted from L1. Hence, the L2 cache in this configuration is also called a victim cache for L1.
Sample Run
The details from Part 1 apply here to the second level L2 cache. Your program gets two separate
configurations (one for level 1 and one for level 2 cache). Both L1 and L2 have the same block size.
Your program should report the total number of memory reads and writes, followed by cache miss
and hit for L1 and L2 cache. Here is the format for part 2.
./second <L1 cache size> <L1 associativity> <L1 cache policy> <L1 block size>
<L2 cache size> <L2 associativity> <L2 cache policy> <trace file>
This is an example testcase for part 2.
./second ** assoc:2 fifo 4 64 assoc:16 lru trace2.txt
memread:**77
memwrite:2**
l1cachehit:6501
l1cachemiss:3499
l2cachehit:222
l2cachemiss:**77
The above example, simulates a 2-way set associate cache of size ** bytes. bytes with block size of
4 for L1 cache. Similarly, L2 cache is a fully associate cache of size 64 bytes. Further, the trace file
used for this run is trace2.txt. As you can see, the program outputs the memory read and memory
writes followed by the L1 and L2 cache hits and misses in the order shown above.
4
Structure of your submission
All files must be included in the pa5 folder. The pa5 directory in your tar file must contain 2
subdirectories, one each for each of the parts. The name of the directories should be named first
and second. Each directory should contain a c source file, a header file (optional) and a Makefile.
To create this file, put everything that you are submitting into a directory named pa5. Then, cd
into the directory containing pa5 (i.e., pa5’s parent directory) and run the following command:
tar cvf pa5.tar pa5
To check that you have correctly created the tar file, you should copy it (pa5.tar) into an empty
directory and run the following command:
tar xvf pa5.tar
This is how the folder structure should be.
* pa5
- first
* first.c
* first.h
* Makefile
- second
* second.c
* second.h
* Makefile
Autograder
First Mode
Testing when you are writing code with a pa5 folder.
• Let us say you have a pa5 folder with the directory substructure as described in the assignment
description.
• copy the pa5 folder to the directory of the autograder.
• Run the autograder with the following command.
python3 pa5_autograder.py
It will run the test cases and print your scores.
5
Second Mode
This mode is to test your final submission (i.e., pa5.tar)
• Copy pa5.tar to the autograder directory.
• Run the autograder with pa5.tar as the argument as shown below
python3 pa5_autograder.py pa5.tar
Grading Guidelines
This is a large class so that necessarily the most significant part of your grade will be based on
programmatic checking of your program. That is, we will build the binary using the Makefile and
source code that you submitted, and then test the binary for correct functionality against a set of
inputs. Thus:
• You should not see or use your friend’s code either partially or fully. We will run state of the
art plagiarism detectors. We will report everything caught by the tool to Office of Student
Conduct.
• You should make sure that we can build your program by just running make.
• Your compilation command with gcc should include the following flags: -Wall -Werror -
fsanitize=address
• You should test your code as thoroughly as you can. For example, programs should not crash
with memory errors.
• Your program should produce the output following the example format shown in previous
sections. Any variation in the output format can result in up to 100% penalty. Be especially
careful to not add extra whitespace or newlines. That means you will probably not get any
credit if you forgot to comment out some debugging message.
• Your folder names in the path should have not have any spaces. Autograder will not work if
any of the folder names have spaces.
Be careful to follow all instructions. If something doesn’t seem right, ask on Canvas discussion
forums or contact the TAs during office hours.
請加QQ:99515681  郵箱:99515681@qq.com   WX:codinghelp

















 

掃一掃在手機打開當前頁
  • 上一篇:CS 2550代做、代寫SQL設計編程
  • 下一篇:菲律賓國旗(國旗的含義是什么)
  • 無相關信息
    合肥生活資訊

    合肥圖文信息
    流體仿真外包多少錢_專業CFD分析代做_友商科技CAE仿真
    流體仿真外包多少錢_專業CFD分析代做_友商科
    CAE仿真分析代做公司 CFD流體仿真服務 管路流場仿真外包
    CAE仿真分析代做公司 CFD流體仿真服務 管路
    流體CFD仿真分析_代做咨詢服務_Fluent 仿真技術服務
    流體CFD仿真分析_代做咨詢服務_Fluent 仿真
    結構仿真分析服務_CAE代做咨詢外包_剛強度疲勞振動
    結構仿真分析服務_CAE代做咨詢外包_剛強度疲
    流體cfd仿真分析服務 7類仿真分析代做服務40個行業
    流體cfd仿真分析服務 7類仿真分析代做服務4
    超全面的拼多多電商運營技巧,多多開團助手,多多出評軟件徽y1698861
    超全面的拼多多電商運營技巧,多多開團助手
    CAE有限元仿真分析團隊,2026仿真代做咨詢服務平臺
    CAE有限元仿真分析團隊,2026仿真代做咨詢服
    釘釘簽到打卡位置修改神器,2026怎么修改定位在范圍內
    釘釘簽到打卡位置修改神器,2026怎么修改定
  • 短信驗證碼 寵物飼養 十大衛浴品牌排行 suno 豆包網頁版入口 wps 目錄網 排行網

    關于我們 | 打賞支持 | 廣告服務 | 聯系我們 | 網站地圖 | 免責聲明 | 幫助中心 | 友情鏈接 |

    Copyright © 2025 hfw.cc Inc. All Rights Reserved. 合肥網 版權所有
    ICP備06013414號-3 公安備 42010502001045

    国产人妻人伦精品_欧美一区二区三区图_亚洲欧洲久久_日韩美女av在线免费观看
    国产成人在线亚洲欧美| 伊人久久大香线蕉成人综合网| 男女猛烈激情xx00免费视频| 日韩精品国内| 欧美一级黑人aaaaaaa做受| 日韩欧美手机在线| 欧美综合在线观看视频| 欧美一区在线直播| 欧美日韩一区二区视频在线观看| 日韩欧美第二区在线观看| 日韩精品在线观看av| 青青在线免费视频| 国内精品视频在线| 国产精品一 二 三| 久久人妻无码一区二区| 久久久久久久久四区三区| 久久久黄色av| 久久成人在线视频| 亚洲一区二区三区视频播放| 亚洲国产精品久久久久婷蜜芽| 亚洲第一在线综合在线| 欧美一区二区三区四区在线 | 亚洲综合日韩中文字幕v在线| 亚洲精品欧美日韩专区| 日韩精品免费一区| 国产视频一区二区视频| 97公开免费视频| 久久九九全国免费精品观看| 久久久久久高潮国产精品视| 日韩av电影免费在线| 欧美大香线蕉线伊人久久国产精品| 国产一区二区三区av在线| 99视频日韩| 国产精品视频一区二区三区四区五区 | 国产在线视频一区| 97色在线播放视频| 按摩亚洲人久久| 亚洲自拍欧美另类| 欧美一区二区影视| 国产精品一区二区三区四区五区| 国产av人人夜夜澡人人爽麻豆| 国产精品久久久久9999小说| 五月天婷亚洲天综合网鲁鲁鲁| 欧美视频第三页| 97免费高清电视剧观看| 国产精品国产三级国产专播精品人 | 成人精品一二区| 久久黄色av网站| 亚州成人av在线| 国产裸体免费无遮挡| 三级精品视频久久久久| 午夜啪啪福利视频| 国产女人18毛片| 久久久久免费看黄a片app| 伊人久久在线观看| 国内自拍在线观看| 久久精品国产精品青草色艺| 中文字幕黄色大片| 精品视频一区二区在线| 久久精品日韩| 亚洲一区二区三区免费观看| 国产日韩一区二区在线观看| 久久天堂电影网| 热草久综合在线| 久久人人爽人人爽人人片av高清 | 精品www久久久久奶水| 国产对白在线播放| 亚洲国产高清国产精品| 国产美女视频免费| 国产精品视频xxx| 日韩欧美一区二区三区久久婷婷 | 欧美日韩精品免费在线观看视频| 91精品久久久久久久久久另类 | 久久精品成人一区二区三区蜜臀| 亚洲精品中文字幕无码蜜桃| 国产日韩欧美在线播放| 国产精品第8页| 欧美日韩一区二区三区在线观看免| 国产精品333| 亚洲av首页在线| 91精品久久久久久蜜桃 | 中文字幕一区二区三区有限公司 | 精品日本一区二区三区在线观看| 日韩在线视频网站| 欧美一区免费视频| 久久天堂av综合合色| 欧美,日韩,国产在线| 国产精品视频一区国模私拍| 国语精品免费视频| 国产精品久久久久久久久久ktv | 中文字幕日本最新乱码视频| 国产精品一区二区三区免费| 欧美日韩国产91| 丰满少妇久久久| 亚洲第一精品区| 国产高清精品一区| 天天人人精品| 久久精品五月婷婷| 秋霞无码一区二区| 国产精品嫩草影院久久久| 国精产品一区一区三区视频| 久久夜色精品亚洲噜噜国产mv| 精品少妇在线视频| 中文字幕日本最新乱码视频| 国产精品10p综合二区| 日韩精品视频在线观看视频| 国产精品爽黄69| 国产免费一区二区| 亚洲人成人77777线观看| 国产国语刺激对白av不卡| 欧美在线影院在线视频| 久久精品视频99| 国产欧美日韩中文字幕在线| 一本色道久久综合亚洲精品婷婷| 91精品啪在线观看麻豆免费| 日韩日韩日韩日韩日韩| 国产成人精品一区二区在线| 狠狠色噜噜狠狠色综合久| 一区二区三区欧美成人| 国产成+人+综合+亚洲欧洲| 欧美连裤袜在线视频| 精品高清视频| 131美女爱做视频| 欧美成人一区二区在线观看| 在线观看成人一级片| 国产不卡精品视男人的天堂| 国产在线拍偷自揄拍精品| 亚洲va久久久噜噜噜| 久久视频中文字幕| 99久久精品免费看国产一区二区三区| 日韩欧美亚洲日产国| 久久成人一区二区| 久久国产精品99久久久久久丝袜| 免费高清在线观看免费| 日韩在线一级片| 久久亚洲综合国产精品99麻豆精品福利| 97福利一区二区| 国语自产精品视频在线看一大j8| 亚洲精品日韩av| 国产精品久久7| 久久久久久久久网| 国产欧美中文字幕| 欧洲成人在线观看| 亚洲欧洲国产精品久久| 国产精品日日摸夜夜添夜夜av| 99在线免费视频观看| 亚洲精品高清视频| 国产精品二区三区| 色狠狠av一区二区三区香蕉蜜桃| 国产精品一区二区三区久久| 欧美亚洲成人网| 日韩一级特黄毛片| 在线视频精品一区| 久久精品一区中文字幕| 国产精品9999久久久久仙踪林| 国产在线日韩在线| 日本一欧美一欧美一亚洲视频| 欧美激情网站在线观看| 久久精品99国产精品酒店日本| 国产高清在线一区二区| 成人中文字幕av| 精品999在线观看| 日本中文字幕成人| 亚洲欧洲在线一区| 精品国产一区二区三区麻豆免费观看完整版 | 99久久国产宗和精品1上映| 黄色小视频大全| 日本高清不卡在线| 日韩一区二区高清视频| 在线播放 亚洲| 国产精品青草久久久久福利99| 国产福利视频一区二区| 国产精品99久久久久久久久| 国产日韩换脸av一区在线观看| 国内精品一区二区三区| 欧美在线日韩在线| 日本精品一区二区三区在线播放视频| 亚洲伊人成综合成人网| 在线观看欧美亚洲| 欧美极品欧美精品欧美视频| 久久亚洲电影天堂| 国产精品久久久久久av| 精品国产欧美成人夜夜嗨| 久久久久日韩精品久久久男男| 国产成人综合久久| 99在线看视频| 97色伦亚洲国产| 97色在线观看免费视频| 国产美女永久无遮挡| 国产日产亚洲精品| 国产日韩二区| 国产免费黄色小视频| 国产欧美日韩一区二区三区| 国产麻豆一区二区三区在线观看 | 国产一区不卡在线观看| 欧美亚洲另类在线一区二区三区| 日韩精品一区二区三区四 | 亚洲综合在线播放| 亚洲熟妇无码一区二区三区| 日韩一级片一区二区|